This invention relates to a semiconductor memory device, such as a DRAM (dynamic random access memory), and more particularly to the activation of column select lines.
FIG. 17 schematically shows the configuration of an ordinary DRAM. The DRAM comprises memory cell arrays (MCA) 171a, 171b, row decoders (RDC) 171c, 171d, row segment selectors (RSS) 171e, 171f, column decoders (CDC) 171g, 171h, 171i, column segment selectors (CSS) 171j, 171k, 171l, a column address buffer (CAB) 171m to which a column address is inputted, a row address buffer (RAB) 171n to which a row address is inputted, a row command buffer (RCB) 171o to which a row-system command is inputted, a column command buffer (CCB) 171p to which a column-system command is inputted, and sense amplifier areas (S/A) 171q, 171r, 171s in which sense amplifiers are placed. On the memory cell arrays 171a, 171b, data line pairs DQ, /DQ (/ denotes an inverted signal) are provided. These data line pairs DQ, /DQ are connected to bit lines via column select gates, which will be explained later.
The memory cell arrays 171a, 171b include memory cells MC, word lines WL for selecting the memory cells, and bit lines BL. On both sides of each of the memory cell arrays 171a, 171b, the sense amplifier areas 171q, 171r, 171s are provided. When more than one row of memory cell arrays exists, a group of memory cell arrays set in the same row is called a row segment and a group of memory cell arrays set in the same column is called a column segment.
The row segment selectors 171e, 171f select a row segment according to a row address. The row decoders 171c, 171d select a word line in the memory cell arrays in the row segment selected by the row segment selectors 171e, 171f. The column segment selectors 171j, 171k, 171l select a column segment in the selected row segment according to a column address and the output signals of the row segment selectors 171e, 171f. The column decoders 171g, 171h, 171i select a column select line CSL in the column segment selected according to the column address and a row address. The selected column select line CSL drives a column select gate (not shown), thereby selecting a bit line BL.
When data is inputted to or outputted from the memory cell arrays 171a, 171b, the row command buffer 171o inputs a command to activate a word line and a row address is inputted to the row address buffer 171n. Part of the row address selects one or more of the row segments and the remaining row address selects one word line in the selected row segment.
For example, as shown in FIG. 18, the DRAM is assumed to have four memory cell arrays MCA0 to MCA3. It is assumed that each memory cell has 512 word lines and two memory cell arrays are activated simultaneously. Eight CSL (column select lines) (not shown) are assumed to be on each sense amplifier area S/A. Row addresses R0 to R8 determine which word line in the row segment should be activated and row address R9 determines which of the consecutive memory cell arrays should be activated. Because there are four memory cell arrays in the example, word lines in the two memory cell arrays MCA0 and MCA2 are activated as shown by solid lines. As a result, the data in the memory cells connected to the activated word lines are read by the sense amplifiers.
To access the data read by the sense amplifiers, a read command is supplied to the column command buffer 171p and a column address is supplied to the column address buffer 171m. The column address determines which sense amplifier should supply the data to the data line pair DQ, /DQ.
Recently, a logic-incorporated memory where a logic circuit has been incorporated into a memory core chip has been developed. Since in the logic-incorporated memory, a large amount of data is transferred between the memory section and logic section, a large I/O width (bit width) is needed. As a result, the number of data lines connected to the input/output terminals is also very large, leading to a large number of column select gates connected to a single column select line CSL. Such a memory often employs an overlaid DQ system in which the data lines are placed above each memory cell array.
FIG. 19 shows an example of the overlaid DQ system. In the overlaid DQ system, many column select gates CSG are connected to a single column select line CSL. As a result, the gate capacitance included in the column decoder and connected to a single driver DRV for driving the column select line becomes very great. The capacitance increases a delay in the transfer of the signal. Consequently, as the signal transmitting over the column select line goes further away from the driver DRV, its waveform becomes duller, which makes a high-speed operation more difficult.
To prevent this, the configuration of FIG. 20 has been considered. In the configuration, blocks of the same construction composed of, for example, a column segment selector CSS, a column decoder CDC, and a driver DRV are placed on both sides of the memory cell arrays MCA. The column select line CSL is driven on both sides. In this case, however, blocks of the same construction have to be placed on both sides of the memory cell arrays. In the case of a complex logic column segment selector CSS, the size of its circuit is large. Consequently, the layout of the blocks requires very large areas, which causes the problem of making the layout size greater.